There are several existing techniques relating to silicon debug. For example, one such technique is referred to as clock-stop and scan-dump (CSSD), in which an application (e.g., one that is known to cause failures) is run as if in normal functional mode. At a pre-determined point in time, clocks are stopped, and once the design is known to be quiescent, the flip-flops (“FFs”) in the design are configured into one or more shift-registers, called “scan-registers” (usually by asserting a “scan-enable” signal). A scan-clock, which may run at a user-defined frequency, is used next to shift out, or “dump” the contents of the FFs for analysis. In many cases, additional logic and fabric resources may be required. For example, in the case of a field-programmable gate array (FPGA), resources such as an Integrated Logic Analyzer (ILA), Joint Testing Action Group (JTAG) interface, and the like may be required. However, the scan registers capture signal values at a particular point in time, and the technique is only useful for addressing structural faults. Thus, it is generally not possible to control status information of an internal signal after a particular event.
Another technique relating to real-time monitoring of hard block signals, e.g., in a transceiver, involves using a first-in first-out buffer to bring the real-time values of the signals out to the programmable fabric of the device. However, from a hard silicon block point of view, this approach is limited to a few clock domains and also requires more logic and verification effort. For example, large clock multiplexers are generally required in connection with this approach, which add clock insertion delays that can affect the performance of the design. Thus, the debugging of integrated circuits continues to be complex and time consuming.
Therefore, it is desirable to provide circuits and methods that facilitate the debugging of integrated circuits.